The worldwide use and methods of manufacturing semiconductors have reached phenomenal proportions over the last decade. Equally phenomenal has been the ever decreasing device size of the semiconductors in general. The on-going trends toward larger wafers, shrinking line widths, and ever thinner oxides are making tight in-line monitoring of wafer cleanliness and uniformity even more critical to semiconductor manufacturers. Contaminants can be any form of matter that causes unintentional changes in electrical properties of semiconductor devices. Some common contaminants include particles, atomic-ionic-molecular defects, and heavy metals.
To prevent contaminants from affecting device performance, a modern fabrication house may involve cleaning steps to remove such contaminants. From a device standpoint, the amount of electrically active impurities in oxides must be minimized because embedded impurities attract or repel free charges in the underlying silicon. In most cases, device performance depends strongly on the concentration of free charges in the silicon, and variations in electrical oxide contamination will usually introduce unwanted variations in device performance. Thus, it is very important to monitor these contaminants and attempt to eliminate them as much as possible from the environment in which the semiconductors are manufactured.
Capacitance-Voltage ("C-V") testing is probably the best known method for detecting oxide processing problems in terms of its charge states and impurities, and for qualifying processes and equipment. Capacitance-Voltage testing is based on measuring the metal oxide silicon ("MOS") capacitance as a function of applied bias to gain important information about the quality and reliability of gate oxides. By performing C-V analysis under temperature and electrical stress, a mobile ion (Q.sub.m) charge component may also be measured separately. However, while C-V techniques are well known and relatively low cost in equipment, the procedure suffers from the disadvantage that the process has a slow test turnaround time, largely due to the added aluminum evaporation or photolithographic patterning required for the test capacitor sample, which slows down production. In addition, these extra steps may actually change the electrical properties of the dielectric due to metal/dielectric reaction and formation of the poly-silicon depletion layer, during MOS capacitor fabrication. Furthermore, for thinner oxide (&lt;30 nm), the C-V technique is problematic due to processing damage induced by sputtering and annealing out the defects. Moreover, the creation of contacts makes reclaiming monitor semiconductor wafers difficult, time-consuming and expensive. Consequently, these wafers are often scrapped after completion of testing, which may significantly increase the materials cost for C-V testing. C-V tests along with J-V and reliability tests have a strong history and demonstrated relevance for oxide quality and end-of-line device performance and reliability. However, because of the time required for such testing, the information obtained from these tests is not available at the desirable time during the fabrication process, for example after gate oxidation.
Corona Oxide Semiconductor ("COS") wafer testing is one of the most promising new techniques on the horizon because it addresses many of the concerns related to C-V testing. This technique requires no physical contact to the wafer, so C-V-like data can be obtained without the added processing time and cost associated with forming MOS contacts. With the C-V technique, test contacts must be applied through a metallization step (or, alternatively, a polysilicon deposition process) before testing. This involves the use of an evaporation mask and an additional anneal step. In addition to increasing the processing time required, these steps erase static charge fingerprints from the wafer, which can provide valuable clues to processing problems. The extra steps required also mean the testing cycle may take from one shift to two days to complete. This difference in time required to perform COS-based test techniques versus traditional C-V-based tests translates into a reduction in process monitoring costs. Furthermore, COS can provide nine-point wafer maps in minutes, while C-V processing often takes hours or days to complete before testing can be started. Therefore, COS also provides a higher fabrication equipment utilization rate, which lowers the overall cost of production. Other benefits include the elimination of additional processing steps, which can mask the original charge conditions, and the capability to reuse the wafer after the induced charge is removed by standard cleaning processes or a deionized water rinse.
In conventional COS, a variety of charge-trapping parameters of the dielectric can be measured, such as the level of mobile charge contamination (Q.sub.m), the degree of density of interface traps (D.sub.it) and the flatband voltage (V)/.sub.fb. These charge-trapping characteristics of the dielectric are important parameters. However, there is a strong demand for non-contact measurements of tunneling and charge-fluence characteristics of these dielectrics to complete the established metrics for dielectrics. The quality of these dielectrics are also strongly coupled to the near-surface defect/impurity characteristics of the semiconductor material (e.g., silicon) underneath.